A Sub-500 mu W Interface Electronics for Bionic Ears

This paper presents an ultra-low power current-mode circuit for a bionic ear interface. Piezoelectric (PZT) sensors at the system input transduce sound vibrations into multi-channel electrical signals, which are then processed by the proposed circuit to stimulate the auditory nerves consistently with the input amplitude level. The sensor outputs are first amplified and range-compressed through ultra-low power logarithmic amplifiers (LAs) into AC current waveforms, which are then rectified through custom current-mode circuits. The envelopes of the rectified signals are extracted, and are selectively sampled as reference for the stimulation current generator, armed with a 7-bit user-programmed DAC to enable patient fitting (calibration). Adjusted biphasic stimulation current is delivered to the nerves according to continuous inter-leaved sampling (CIS) stimulation strategy through a switch matrix. Each current pulse is optimized to have an exponentially decaying shape, which leads to reduced supply voltage, and hence similar to 20% lower stimulator power dissipation. The circuit has been designed and fabricated in 180nm high-voltage CMOS technology with up to 60 dB measured input dynamic range, and up to 1 mA average stimulation current. The 8-channel interface has been validated to be fully functional with 472 mu W power dissipation, which is the lowest value in the literature to date, when stimulated by a mimicked speech signal

A fully integrated autonomous power management system with high power capacity and novel MPPT for thermoelectric energy harvesters in IoT/wearable applications

This paper reports a fully integrated autonomous power management system for thermoelectric energy harvesting with application in batteryless IoT/Wearable devices. The novel maximum power point tracking (MPPT) algorithm does not require open circuit voltage measurement. The proposed system delivers 0.5 mA current with 1 V regulated output based on simulations, which is the highest output current for a fully integrated converter reported in the literature for ultra-low voltage applications, to the best knowledge of the authors. Regulated 1 V output can be achieved for load range >2 k Omega, and input voltage range >140 mV. The circuit has been implemented in UMC-180nm standard CMOS technology and simulated

Physiological parameters for Prognosis in Abdominal Sepsis (PIPAS) Study : a WSES observational study

BackgroundTiming and adequacy of peritoneal source control are the most important pillars in the management of patients with acute peritonitis. Therefore, early prognostic evaluation of acute peritonitis is paramount to assess the severity and establish a prompt and appropriate treatment. The objectives of this study were to identify clinical and laboratory predictors for in-hospital mortality in patients with acute peritonitis and to develop a warning score system, based on easily recognizable and assessable variables, globally accepted.MethodsThis worldwide multicentre observational study included 153 surgical departments across 56 countries over a 4-month study period between February 1, 2018, and May 31, 2018.ResultsA total of 3137 patients were included, with 1815 (57.9%) men and 1322 (42.1%) women, with a median age of 47years (interquartile range [IQR] 28-66). The overall in-hospital mortality rate was 8.9%, with a median length of stay of 6days (IQR 4-10). Using multivariable logistic regression, independent variables associated with in-hospital mortality were identified: age > 80years, malignancy, severe cardiovascular disease, severe chronic kidney disease, respiratory rate >= 22 breaths/min, systolic blood pressure 4mmol/l. These variables were used to create the PIPAS Severity Score, a bedside early warning score for patients with acute peritonitis. The overall mortality was 2.9% for patients who had scores of 0-1, 22.7% for those who had scores of 2-3, 46.8% for those who had scores of 4-5, and 86.7% for those who have scores of 7-8.ConclusionsThe simple PIPAS Severity Score can be used on a global level and can help clinicians to identify patients at high risk for treatment failure and mortality.Peer reviewe

Nurses' perceptions of aids and obstacles to the provision of optimal end of life care in ICU

Contains fulltext : 172380.pdf (publisher's version ) (Open Access

PETAM: Power Estimation Tool for Array Multipliers

Increasing demand for the mobile, low energy systems has laid emphasis on the development of low power processors. Low power design has to be incorporated into fundamental computation units, such as multipliers. The optimization of the energy-delay product in such low power multipliers will enable energy efficient computation. This study proposes a power estimation tool to analyze different array multiplier architectures, which are most commonly used in such applications. Gate level library design parameters are utilized to derive energy-delay performance for any given set of input vector patterns, and multiplier size. Vector and size dependent factors are therefore clearly identified. Examples are provided from carry save array multiplier (CSAM) and ripple carry array multiplier (RCAM) to demonstrate the capabilities for the tool

Power-Delay Analysis of an ABACUS Parallel Integer Multiplier VLSI Implementation

ABACUS parallel architecture was previously proposed as an alternate integer multiplication approach with column compression and parallel carry futures. This paper presents a VLSI implementation for ABACUS and benchmarks it against the conventional Wallace Tree Multiplier (WTM). Simulations are conducted with UMC180nm technology in Cadence environment. Although WTM implementation results in 26.6% fewer devices, ABACUS implementation has 8.6% less power dissipation with matched delay performance, due to 27.8% lower average activity

Comparative Power-Delay Performance Analysis of Threshold Logic Technologies

Recent focus in energy efficiency is motivated with diminishing conventional energy resources, and increasing demand in low power applications with shrinking platform sizes. In this work, various threshold logic technologies are compared with each other in terms of power-delay-product (PDP). Compound CMOS, complementary pass transistor, static NAND gate, full adder, capacitive and differential threshold logic technologies are compared within a developed comparison scenario. Results in UMC180nm technology indicate that complementary pass transistor based threshold logic proves at least 2.5% more efficient than the rest in terms of PDP, while NAND based implementation has 29.2% better in terms of delay performance

Patient-Centered Design Method for Self-Powered and Cost-Optimized Health Monitors

The emergence of Wireless Body Area Networks (WBANs) with health monitoring capabilities has revolutionized health care. Implementing fully independent WBAN nodes is important to the long-term viability of this initiative. Regularly recharged and depletable batteries remain a significant impediment in such systems. Energy harvesting (EH) from environmentally clean sources has thus been receiving increasing attention. Nevertheless, the autonomy and optimization of existing WBAN sensor nodes have remained questionable because methods that integrate realistic usage conditions into the design process have been lacking. A plausible method is proposed to establish a framework for designing a sustainable health monitoring node in this work. A Health Monitoring Energy System (HeMeS) tool prototype is consequently developed using comprehensive analytical models and utilized to demonstrate system design space exploration for various patient types, incorporating environmental factors, electronic load activity levels, and system cost/size constraints. It is concluded that the patient-centered system design approach incorporating interactions across transducers, electronics, sensors, user environment and data duty-cycling profiles, is viable, and is in fact appealing in safeguarding truly autonomous and cost-optimal WBANs that are compatible with climate-neutral society